Memory Hierarchy and Access Time - Sand, Software Program And Sound > 자유게시판

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This web page takes a closer look on the Raspberry Pi Memory Wave focus enhancer hierarchy. Every stage of the memory hierarchy has a capability and velocity. Capacities are comparatively straightforward to find by querying the working system or studying the ARM1176 technical reference handbook. Pace, nevertheless, is not as simple to discover and must usually be measured. I use a simple pointer chasing method to characterize the behavior of each stage within the hierarchy. The method also reveals the conduct of memory-related performance counter occasions at each degree. The Raspberry Pi implements 5 levels in its memory hierarchy. The levels are summarized within the desk beneath. The highest degree consists of digital memory pages that are maintained in secondary storage. Raspbian Wheezy retains its swap house within the file /var/swap on the SDHC card. That is sufficient house for 25,600 4KB pages. You are allowed as many pages as will match into the preallocated swap space.

The Raspberry Pi has either 256MB (Mannequin A) or 512MB (Model B) of primary memory. That is sufficient area for 65,536 pages or 131,072 bodily pages, if all of major memory have been out there for paging. It isn’t all obtainable for consumer-house applications because the Linux kernel wants area for its personal code and data. Linux additionally helps large pages, but that’s a separate subject for now. The vmstat command displays details about virtual memory utilization. Please confer with the man page for utilization. Vmstat is a good software for troubleshooting paging-associated performance points because it shows page in and out statistics. The processor in the Raspberry Pi is the Broadcom BCM2835. The BCM2835 does have a unified level 2 (L2) cache. Nevertheless, the L2 cache is devoted to the VideoCore GPU. Memory references from the CPU aspect are routed across the L2 cache. The BCM2835 has two degree 1 (L1) caches: a 16KB instruction cache and a 16KB data cache.

Our analysis beneath concentrates on the info cache. The data cache is 4-method set associative. Each method in an associative set shops a 32-byte cache line. The cache can handle as much as 4 active references to the identical set without conflict. If all four ways in a set are legitimate and a fifth reference is made to the set, then a conflict occurs and one of many four methods is victimized to make room for the new reference. The information cache is just about indexed and physically tagged. Cache lines and tags are stored individually in DATARAM and TAGRAM, respectively. Virtual handle bits 11:5 index the TAGRAM and DATARAM. Given a 16KB capability, 32 byte lines and four ways, there should be 128 units. Digital tackle bits 4:Zero are the offset into the cache line. The data MicroTLB interprets a virtual handle to a bodily tackle and sends the bodily tackle to the L1 knowledge cache.

The L1 information cache compares the bodily tackle with the tag and determines hit/miss standing and the proper way. The load-to-use latency is three (3) cycles for an L1 data cache hit. The BCM2835 implements a two level translation lookaside buffer (TLB) construction for digital to physical address translation. There are two MicroTLBs: a ten entry data MicroTLB and a ten entry instruction MicroTLB. The MicroTLBs are backed by the principle TLB (i.e., the second degree TLB). The MicroTLBs are totally associative. Every MicroTLB interprets a virtual address to a physical deal with in one cycle when the web page mapping info is resident in the MicroTLB (that's, successful in the MicroTLB). The primary TLB is a unified TLB that handles misses from the instruction and data MicroTLBs. A 64-entry, 2-method associative structure. Foremost TLB misses are handled by a hardware page table walker. A web page table stroll requires a minimum of one further memory access to search out the page mapping data in primary memory.